1. Field of the Invention
The present invention relates to a voltage comparator and a subranging A/D converter including such a voltage comparator.
2. Description of the Background Art
An A/D converter converts an analog signal to a digital signal. There are flash A/D converters, subranging A/D converters, etc. A subranging A/D converter A/D-converts an analog signal in two stages, i.e. stages of more significant bits and less significant bits. This subranging A/D converter has a smaller circuit scale and smaller power consumption as compared to a flash A/D converter. The subranging A/D converter is suited for installation in an LSI (Large Scale Integrated circuit) or a VLSI (Very Large Scale Integrated circuit) for this characteristic. This advantage of the series-parallel type has recently accelerated its development. An example of a subranging A/D converter as described above is presented in a document entitled "A CMOS 40 MHz 86 105 mW Two-Step ADC", IEEE ISSCC Dig. of Teach. Papers. pp. 14-15, 1989.
FIG. 12 is a block diagram showing the conventional subranging A/D converter disclosed in the above-stated document. The subranging A/D converter shown in FIG. 12 conducts A/D conversion of a total of m+n bits formed of more significant m bits and less significant n bits. Referring to FIG. 12, the subranging A/D converter includes a reference voltage generation circuit 1, coarse voltage comparators A.sub.0 -A.sub.k-1 (k=2.sup.m 1), a coarse encoder 2 for encoding m bits, fine voltage comparators B.sub.0 -B.sub.l-1 (l.gtoreq.2.sup.n -1), a fine encoder 3 for encoding n bits, and an error correction circuit 4. The reference voltage generation circuit 1 has two input terminals 5 and 6 for applying reference voltages Vrt and Vrb, and an input terminal 7 for controlling a signal. The reference voltage generation circuit 1 has k coarse reference voltage output terminals a.sub.0 -a.sub.k-1 and l fine reference voltage output terminals b.sub.0 -b.sub.l-1 for outputting analog voltages based on these input voltages or input signals. The coarse voltage comparators A.sub.i (i=0 to k-1) each has 2 input terminals, one of which is connected together to an analog voltage application terminal 8, the other is connected to the coarse reference voltage output terminal a.sub.i. The coarse encoder 2 has k input terminals connected to the outputs of k coarse voltage comparators a.sub.i, a 4 bit encoder result output terminal for outputting an encoder result, and an output terminal for control. The terminal to output an encoder result is connected to the input terminal of the error correction circuit 4, the output terminal for control signal is connected to the input terminal for control signal 7 of the reference voltage generation circuit 1. As is the case with the coarse voltage comparator A.sub.i, the fine comparators Bj (j=0 to l-1) each have 2 input terminals, one of which is connected together to the analog voltage application terminal 8, and the other is connected to the fine reference voltage output terminal b.sub.j. The fine encoder 3 has l input terminals connected to the outputs of the fine voltage comparators B.sub.j, an output terminal 9 for outputting an encode result of n bits, and an error detection signal output terminal 10 for outputting an error detection signal to the error correction circuit 4. The error correction circuit 4 has m input terminals connected to the output of coarse encoder 2, an input terminal connected to the error detection signal output terminal 10, and an output terminal 11 for outputting a final coarse encoder result of m bits which has been subjected to error correction.
An operation of the subranging A/D converter shown in FIG. 12 will be described. The subranging A/D converter operates in two stages, in other words in stages of coarse A/D conversion and fine A/D conversion. In the first stage, in other words in the coarse A/D conversion stage, each of the coarse voltage comparators A.sub.i compares an analog signal voltage Vin and a coarse reference voltage Va.sub.i output from the coarse reference voltage input terminal a.sub.i. The coarse reference voltage Va.sub.i is usually obtained by dividing the two voltages Vrt and Vrb applied to the reference voltage application terminals 5 and 6 of the reference voltage generation circuit 1. Such reference voltage Va.sub.i and the analog signal voltage Vin are compared at the voltage comparator, and a range of voltage in which the analog voltage Vin exists is detected, and then a conversion into a desired code is conducted at the encoder 2. At the same time, a detection signal of the above-stated voltage range is applied to the control signal input terminal 7 of the reference voltage generation circuit 1.
In the second stage, in other words in the fine A/D conversion stage, a fine reference voltage Vb.sub.j to be output to the fine reference voltage application terminal B.sub.j is generated by the reference voltage generation circuit 1 based on a control signal. For example, if the presence of the analog signal voltage Vin between the coarse reference voltages Va.sub.i and Va.sub.i+1 in the course of a coarse A/D conversion, a voltage further divided including both voltages is generated. Thus generated fine reference voltages V.sub.bj are each input into one input end of a corresponding voltage comparator B.sub.j. The analog signal voltage Vin is applied in common to the other input end of each of the voltage comparators B.sub.j, comparison and encoding are conducted as is the case with the coarse A/D conversion operation, and finally a fine A/D conversion result in a desired code is output from the terminal 9. At the same time, a determination is made whether or not the range in which the analog signal voltage Vin detected in the fine A/D conversion exists coincide with that of the coarse A/D conversion result, and if no coincidence is found, a control signal is transferred to the error correction circuit 4 through the error detection signal output terminal 10. The error correction circuit 4, based on the control signal, corrects the coarse encoder result, and finally outputs a coarse A/D conversion result to the terminal 11.
FIG. 13 is a circuit diagram showing an example of a conventional 2-input voltage comparator. Referring to FIG. 13, in the voltage comparator, a coarse voltage comparator A.sub.i and a fine voltage comparator Bj are independently provided. The voltage comparator is controlled by clock signals .phi..sub.1 -.phi..sub.31 generated by a clock signal generation circuit 50 externally provided.
The coarse voltage comparator A.sub.i is formed of a series-connection of an input circuit 12, amplification circuits 13a and 14a of first and second stages having an automatic zero compensation function, and an inversion amplifier 15a. The input circuit 12 includes a switch S1 connected to an analog signal application terminal 8, and a switch S2 connected to a coarse reference voltage application terminal a.sub.i. The switch S1 is turned on/off in response to the clock signal .phi.1. The switch S2 is turned on/off in response to the clock signal .phi.2. The output terminals of the switches S1 and S2 are connected together to the input end of the first stage amplification circuit 13. The first stage amplification circuit 13 includes a coupling capacitor Cc, an inversion amplifier 16, and a switch S3 connected between the input and output of the inversion amplifier 16. The coupling capacitor Cc has one end connected to the output of the input circuit 12 and the other end connected to the input of the inversion amplifier 16. The switch S3 is turned on/off in response to the clock signal .phi.1. When the switch S3 conducts, the output of the inversion amplifier 16 is fed back to the input of the amplifier 16. The second stage amplification circuit 14a has the same construction as that of the first amplification circuit 13.
As is the case with the coarse voltage comparator A.sub.i, a fine voltage comparator B.sub.j is formed of a series-connection of an input circuit 17, first stage and second stage amplification circuits 13b and 14b, and an inversion amplifier 15b. An essential difference from the coarse voltage comparator A.sub.i is that the input circuit 17 is connected to the fine reference voltage output terminal b.sub.j (see FIG. 12), and the fine reference voltage output terminal b.sub.j is connected to the input end of the first stage amplification circuit 13b through a switch S4. The switch S4 is turned on/off in response to the clock signal .phi.3.
FIG. 14 is a representation showing the signal waveforms of the circuits shown in FIG. 13. The waveforms of V.sub.3, V.sub.4, V.sub.5 indicated by the solid lines in FIG. 14 are voltage waveforms in the coarse comparison, while the waveforms of V.sub.3, V.sub.4, V.sub.5 depicted by the chain dotted lines are voltage waveforms in the fine comparison. Referring to FIG. 14, a description of an operation of the coarse voltage comparator A.sub.i shown in FIG. 13 follows. In a period when the clock signal .phi.1 is in an "H" level (this period is referred to as an auto zero period), the switches S1 and S3 are turned on, while the switch S2 is turned off. With the switch S1 made conductive, the analog signal voltage Vin is applied to the first stage amplification circuit 13a. With the switch S3 made conductive, the outputs of the internal nodes N1 and N2 of first stage and second stage amplification circuits 13a and 14a are biased to the logic threshold voltage Vb of the inversion amplifier 16. Thus, charges are accumulated on the internal nodes N1 and N2 of the first stage and second stage amplification circuits 13a and 14a. Assuming that the accumulated charges are Q and Q.sub.2, respectively, and the parasitic capacitance of nodes N1 and N2 are Cs and Cs.sub.2, respectively, the following equations hold. EQU Q.sub.1 =PCc (Vb-V.sub.in)+C.sub.s1 Vb (1) EQU Q.sub.2 =PCc (Vv-V.sub.b)+C.sub.S2 Vb (2)
At the same time, the output of the inversion amplifier 15a is also biased to the threshold Vb.
In a period when the clock signal .phi.2 is in an "H" level (this period is referred to as coarse comparison period), the switch S2 is turned on, while the switches S1 and S3 are turned off. With the switch S3 conducting, the first stage and second stage amplification circuits 13a and 14a lose an inlet and outlet path for charges to and from the internal nodes N1 and N2, and the charges Q.sub.1 and Q.sub.2 accumulated in the auto zero period are held therein. Meanwhile, the coarse reference voltage Va.sub.i rather than the analog signal voltage Vin is applied to the input terminal of the first stage amplification circuit 13a of the coarse voltage comparator A.sub.i in this period. Thus, the voltages of the internal nodes N1 and N2 of the first stage and second stage amplification circuits 13a and 14a change its level from the threshold voltage Vb to certain voltages V.sub.1 and V.sub.2. Accordingly, the amount of charge Q at the internal node N1 of the first stage amplification circuit 13 is given by the following equation using the voltage V.sub.1. EQU Q.sub.1 =Cc (V.sub.1 -Va.sub.i)+Cs.sub.1 V.sub.1 ( 3)
Therefore, from equations (1) and (3), the voltage V.sub.1 is finally given by the following equation. EQU V.sub.1 =Vb+.lambda.(Va.sub.i -V.sub.in) (4)
where, EQU .lambda.=Cc/(Cc+Cs) (5)
Equation (4) means that the voltage of the internal node N1 of the first stage amplification circuit 13a shifts from the threshold voltage Vb in response to a voltage change (this proportion amount is referred to as a voltage transmission rate) generated at the input. More specifically, the amount of voltage change created on the input side by the coupling capacitor Cc and the parasitic capacitor Cs is multiplied by .lambda., and the .lambda.-multiplied voltage change is superimposed to the threshold voltage Vb. Now, assuming that the voltage change on the input side is .DELTA.Vin, the voltage on the output side before this voltage change is transferred is Vout.sub.0, the voltage on the output side after the transfer is Vout, Vout is generally given by the following equation EQU Vout=Vout.sub.0 +.lambda..DELTA.Vin (6)
Accordingly, the input of the first stage amplification circuit 13a is shifted from the threshold voltage Vb by .lambda..DELTA.Vic (where .DELTA.Vic=Va.sub.i -Vin; coarse input differential voltage). Such shift amount is amplified by the inversion amplifier 16 of the first stage amplification circuit 13a. When the voltage amplification factor of the inversion amplifier 16 is -G and the output voltage is V.sub.3, the output voltage V.sub.3 is given by the following equation: EQU V.sub.3 =Vb-.lambda.G.DELTA.Vic (7)
In the second stage amplification circuit 14, the above-stated voltage V.sub.3 is applied rather than the threshold voltage Vb in the auto zero period. The application of the output voltage V.sub.3 changes the voltage of the internal node N2 from Vb. The amount of this voltage change can be produced based on the principle of conservation of charge in the input node N2, but herein, only the result is given based on equation (6). More specifically, the voltage change .DELTA.V.sub.3 on the input side of the second stage amplification circuit 14 is -.lambda.G.DELTA.Vic from equation (7), and therefore the voltage change .DELTA.V.sub.2 generated at the node N2 is given by the following equation: EQU .DELTA.V.sub.2 =.lambda..DELTA.V.sub.3 =-.lambda..sup.2 G.DELTA.Vic (8)
This voltage change .DELTA.V.sub.2 is further amplified by the inversion amplifier 16 of the second stage amplification circuit 14a. The voltage change .DELTA..sub.V4 in the output end of the inversion amplifier 16 is given by the following equation: EQU .DELTA..sub.V.sub.4 =-G.DELTA.V.sub.2 =.lambda..sup.2 G.sup.2 .DELTA.Vic (9)
This is further amplified by the inversion amplifier 15a, and, therefore, the output voltage V.sub.5 of the amplifier 15a is given by the following equation: EQU V.sub.5 =Vb-G.DELTA.V.sub.4 =Vb-.lambda..sup.2 G.sup.3 .DELTA.Vic (10)
Equation (10) indicates that the coarse input differential voltage .DELTA.Vic is multiplied by .lambda..sup.2 G.sup.3 for output in the coarse voltage comparator A.sub.i. Accordingly, if, for example, .lambda.=1, G=10, Vb=2.5 V, and an input differential voltage is equal to or larger than 1.7 mV, amplification can be made up to a logic level ("H" is more than 4.2 V, while "L" is less than 0.8 V with a power supply voltage of 5 V). At that time, the voltage comparator outputs an "H" level when Vin&gt;Va.sub.i, and an "L" level when Vin&lt;Va.sub.i. Based on this output result (comparison result) the reference voltage generation circuit 1 generates the fine reference voltage Vb.sub.j, and applies the generated voltage to the fine reference voltage application terminal b.sub.j.
The fine voltage comparator B.sub.j operates based on the same principle as the coarse voltage comparator A.sub.i with only the difference being that comparison is conducted when the clock signal .phi.3 is in an "H" level (this is called fine comparison period). Therefore, description will not be repeated here.
As described above, when the conventional 2-input voltage comparator is used in a subranging A/D converter, it is necessary to separately provide a voltage comparator for coarse A/D conversion and a voltage comparator for fine A/D conversion. As described above, the subranging A/D converter conducts series-parallel A/D conversion in two stages, and as is well known the converter needs at least 2.sup.m -1 voltage comparators for a parallel A/D conversion of, for example, m bits. Accordingly, with increase of resolution, the number of voltage comparators necessary increases as an exponential rate. In order to alleviate such disadvantage of the subranging A/D converter, use of a 3-input voltage comparator is proposed in an article entitled "An 8-bit 20 MS/s CMOS A/D Converter with 50-mW Power Consumption" IEEE Journal of Solid State Circuit 1990 Vol. 25, No. 1 pp. 167-172.
FIG. 15 is a circuit diagram showing the 3-input voltage comparator disclosed in the above-stated article, and FIG. 16 is a representation showing the signal waveforms of the circuits in FIG. 15. The voltage comparator shown in FIG. 15 is different from the voltage comparator shown in FIG. 13 in that a three-input input circuit 19 is used instead of two 2-input input circuits 12 and 17, and first stage and second stage amplification circuits 13 and 14, and the inversion amplifier 15 are provided one for each. The input circuit 19 includes three input terminals, an analog signal application terminal 8, a coarse reference voltage application terminal a.sub.i and a fine reference voltage application terminal b.sub.j. The input terminals 8, a.sub.i and b.sub.j are connected together to the input end of the first stage amplification circuit 13 respectively through switches S1, S2 and S4. The switch S1 is turned on/off in response to the clock signal .phi.1. The switch S2 is turned on/off in response to the clock signal .phi.2. The switch S4 is turned on/off in response to the clock signal .phi.3.
A description of an operation follows. The voltage comparator is controlled by the clock signals shown in FIG. 16 (the same as those shown in FIG. 14), and operates in three stages. When the clock signal .phi.1 is in an "H" level (auto zero period), the switches S1 and S3 are turned on, while the switches S2 and S4 are turned off. With the switch S1 being turned on, the analog signal voltage Vin is applied to the input of the first stage amplification circuit 13. With the switch S3 being turned on, the internal nodes N1, N2 and outputs of the first stage and second stage amplification circuits 13 and 14 are biased to the logic threshold voltage Vb of the inversion amplifier 16. The output of the inversion amplifier 15 is biased to the voltage Bb accordingly.
In a period when the clock signal .phi.2 is of "H" level (coarse comparison period), only the switch S2 is turned on, and the other switches S1, S3, and S4 are turned off. The operation in this case is the same as the above-stated voltage comparator (FIG. 13), a description will not be repeated here.
In a period when the clock signal .phi.3 is of "H" level (fine comparison period), the switch S4 is turned on, and the other switches S1-S3 are turned off. Also in this period, with the switch S3 still being turned off, the internal nodes N1 and N2 of the first stage and second stage amplification circuits 13 and 14 attain a high impedance state. Therefore, in the auto zero period, charges accumulated at the internal nodes N1 and N2 are still conserved in this period, and equation (6) given above holds in this period. Meanwhile, with the switch S4 being turned on, the fine reference voltage Vbj instead of the coarse reference voltage Va.sub.i is applied to the input of the first stage amplification circuit 13. The voltage obtained by multiplying this voltage change (Vb.sub.j -Va.sub.i) by .lambda. is superimposed to the voltage V.sub.1 produced by equation (4). Accordingly, the voltage V.sub.11 of the node N3 of the amplification circuit 13 in the fine comparison period is given by the following equation: ##EQU1##
Equation (11) indicates that voltage change from Vin to the fine reference voltage Vb.sub.j takes place at the input end of the first stage amplification circuit 13. The voltage shift from the logic threshold voltage Vb is transferred to succeeding stages as is the case with the voltage comparator shown in FIG. 13, and a fine comparison is conducted. When the voltage comparator is constructed as shown in FIG. 15, the coarse and fine voltage comparisons can be conducted in a single voltage comparator. Therefore, A/D conversion of a total of 2m bits formed of more significant m bits and less significant m bits is conducted, (2.sup.m -1) voltage comparators may be provided. This means that the number of voltage comparators necessary is reduced by half as compared to the 2-input voltage comparator (FIG. 13) which requires 2.multidot.(2.sup.m -1) voltage comparators. The voltage comparator of this construction however still suffers from the following disadvantage.
This disadvantage will be described in conjunction with the output transient responsive waveforms of the amplification stages of fine voltage comparator Bj and the transient responsive waveforms of the amplification stages of the 3-input voltage comparator shown in FIG. 16. In FIGS. 14 and 16, V3 represents the output voltage of the first stage amplification circuit 13, V4 the output voltage of the second stage amplification circuit 14, and V5 the output voltage of the inversion amplifier 15. As can be seen from FIG. 14, all the internal nodes N1-N4 are biased to the threshold voltage Vb immediately before fine comparison in the 2-input voltage comparator (this state is referred to as initial state), the internal nodes N1-N4 start responding for outputting a correct comparison result the moment the fine reference voltage Vb.sub.j is supplied. In contrast, in the 3-input voltage comparator, the internal nodes have shifted from the logic threshold voltage Vb immediately before execution of the fine comparison depending upon the coarse comparison result. Accordingly, the 3-input voltage comparator requires an extra time period (this is referred to as recovery time) until the voltage at the end of the coarse comparison returns to the initial state. For example, in the first stage amplification circuit 13, time until the output voltage V3 crosses the logic threshold voltage Vb is the recovery time of the amplification circuit 13. The output voltage V4 of the second stage amplification circuit 14 begins to be inverted at the moment the output voltage of the first stage amplification circuit 13 crosses Vb. Therefore, the recovery time of the amplification circuit 14 is produced as the sum of the recovery time of the first stage amplification circuit 13 and its recovery time. Recovery time increases in succeeding stages, which results in degradation in the comparison speed for the entire voltage comparator.
Additionally, in the conventional 2-input and 3-input voltage comparators, comparison accuracy sometimes degrades due to a clock noise. A transmission gate as shown in FIG. 17 is generally used for the switches S1-S4 in the voltage comparators shown in FIGS. 13 and 15. The transmission gate includes a PMOS transistor 20, and an NMOS transistor 21 connected in parallel thereto. The PMOS and NMOS transistors 20 and 21 have their gate terminals 22 and 23 supplied with clock signals which are complementary to each other. The drain electrodes and source electrodes of the transistors 20 and 21 are connected together to terminals 24 and 25, respectively. Gate-drain capacitors 26 and 27 of capacitance values C.sub.1 and C.sub.2 exist in a parasitic manner between the gate electrodes 22, 23 and drain electrodes 24 of the transistors 20, 21. Similarly, gate-source capacitors 28 and 29 of capacitance values C.sub.3 and C.sub.4 exist in a parasitic manner between the gate electrodes and source electrodes of transistors 20 and 21.
Now, an operation of the transmission gate taking into account the parasitic capacitance will be described. When a signal applied to the gate electrode 22 changes its level from "L" to "H", and a signal applied to the gate electrode 23 changes its level from "H" to "L", the transmission gate is turned off. This gate voltage change is transferred to the terminals 24 and 25 through the parasitic capacitor. More specifically, charge is implanted into terminals 24 and 25 by the change of the gate voltage. When the terminals 24 and 25 are in the state of high impedance, a minor voltage change takes place by the implanted charge. When a signal of a large amplitude is dealt with as in the case of a digital circuit, such minor voltage change does not cause any problem, but results in a significant problem in an analog circuit.
Now, an operation of the 2-input coarse voltage comparator A.sub.i taking into such implanted charge will be described. Consider, for example, the switch S3 of the first stage amplification circuit 13a shown in FIG. 13. When the switch S3 is formed of a transmission gate, it generates a voltage change caused by the change of the clock signal at the internal node N2 at the moment it is turned off. The voltage change .DELTA.V.sub.21 of the internal node N2 caused exclusively by this clock change is given by the following equation, wherein the gate terminal voltage of a P type transistor is .DELTA.Vclk, and the gate terminal voltage of an N type transistor is -.DELTA.Vclk: ##EQU2##
Therefore, the voltage V.sub.1 of the internal node N1 in the first stage amplification circuit 13 in the coarse comparison period when such clock noise is taken into account is given by the following equations: EQU V.sub.1 =Vb+.lambda..DELTA.Vic+.lambda.C.DELTA.Vclk (13)
, where EQU .lambda.C.fwdarw.(C.sub.1 -C.sub.2)/(Cc+Cs.sub.1) (14
From the above equations, when, for example, .DELTA.Vic=-1 mV, and .DELTA.Vclk=5 V, and the following expression holds: EQU C.sub.1 -C.sub.2 &gt;Cc/5000 (15)
This indicates that an erroneous operation is caused by the clock noise. When expression (15) is satisfied, V.sub.1 -Vb&gt;0 is true despite that .DELTA.Vic&lt;0. In order to prevent such erroneous operation, if Cc=0.1 fF, the expression C.sub.1 -C.sub.2 &lt;0.02 fF or smaller must be satisfied. C.sub.1 and C.sub.2 are parasitic capacitors, and, therefore, it is difficult to control the capacitance values in the above-stated order. Upon occurrence of an erroneous operation in the first stage amplification circuit 13, this error is amplified and output as a comparison result. Such clock noise is also generated in the second stage amplification circuit 14, but the signal has already been amplified at the first stage amplification circuit 13, and therefore does not cause such a significant problem as compared to the first stage.
With the conventional 2-input voltage comparator constructed as in the above-described manner, the number of voltage comparators necessary when an A/D converter is formed using such voltage comparators increases as an exponential function with increase of the resolution of A/D converter. Also, the conventional 3-input voltage comparator alleviates the above-stated problem, but its comparison speed decreases. Furthermore, both 2-input and 3-input voltage comparators are prone to erroneous operations caused by clock noises, and both have problems in the comparison accuracies.